In many applications semiconductor integrated circuit chips are mounted to chip packages which are then connected to a motherboard having a number of chip packages. Thus, there are two levels of interconnection. In the first level, one or more integrated circuit chips are electrically connected to the package. Common techniques for achieving the chip-to-package interconnection include wire bonding, flip-chip processing and tape automated bonding.
The second level of interconnection provides electrical connection between the chip package and the motherboard. The most common packages are dual-in-line packages (DIP), pin-grid array packages, leadless chip carriers, and leaded chip carriers. DIP packages have leads that extend from the sides of the package for insertion into throughholes in the motherboard. The leads are then soldered to form interconnection points between the DIP package and the motherboard. Such packages are satisfactory for leadouts of up to approximately eighty leads. Pin-grid packages provide a higher lead density, since the pins are placed in a regular x-y array along a major surface of the pin-grid package.
A leaded chip carrier typically includes a carrier board onto which one or more chips are mounted. The second level of interconnection, i.e. the package-to-motherboard connection, then entails linking contact sites on the carrier board to contact sites on the motherboard. This can be achieved by using the same techniques as those used at the chip-to-package interconnection level. That is, second level interconnection schemes include wire bonding miniature wires and include tape automated bonding a frame of leads from contact sites on the carrier board to contact sites on the motherboard. The connection of the miniature wires or the frame of leads increases the cost of chip carrier fabrication. Moreover, misalignment of the wires or leads and improper soldering of the individual leads often result in defective operation of the resulting device. Thus, the second level interconnect members affect reliability and fabrication yield.
Leadless chip carriers are known, but often include cost-inefficient fabrication steps for exposing contact sites on the chip carrier for solder connection to contact sites on the motherboard. For example, conductors may be formed within grooves extending vertically along the edges of the chip carrier substrate for solder connection to the motherboard.
It is an object of the present invention to provide a method of forming leadouts on a surface mountable chip carrier for electrical interconnection to a supporting substrate such as a motherboard, wherein testing, reliability and yield are enhanced and cost is reduced.